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Cloud toolchains & CubeMX

The tools that normally need a beefy workstation and a tangle of licenses run on Subaya’s backend instead. You drive them through the CLI and pay only for the compute seconds you use.

Cloud-hosted tools

Section titled “Cloud-hosted tools”

Heavy tools run on Subaya’s backend, not your laptop:

  • Quartus — Intel/Altera FPGA synthesis.
  • RyuSim — Subaya’s SystemVerilog simulator.
  • Renode — embedded system emulation.
  • BitCrucible — hardware validation bridge.
  • headless CubeMX — the authoritative validation and code-generation engine behind Subaya’s embedded pin-planning surface.

You never install these locally — the backend is the authoritative environment. See Billing & usage for how the metered compute works.

Embedded pin-planning with suya arch

Section titled “Embedded pin-planning with suya arch”

For embedded (e.g. STM32) projects, Subaya exposes a pin-planning surface backed by the headless CubeMX engine. A pin-plan captures the MCU/board, pin assignments, peripheral configs, and clock-tree intent, and generates a CubeMX .ioc project file.

For a full worked example, see STM32 getting started.

Create a pin-plan

Section titled “Create a pin-plan”

Start a plan from a supported dev board (the board contract gives you the LED, button, and virtual-COM-port pins for free) or from a bare MCU part:

Terminal window
# From a supported dev board
suya arch pin-plan create --board NUCLEO-L433RC-P


# …or from a bare MCU part
suya arch pin-plan create --mcu STM32F407VGTx

List and inspect plans:

Terminal window
suya arch pin-plan list
suya arch pin-plan show --plan <plan-id>

Set pins

Section titled “Set pins”

Assign a signal to a physical pin:

Terminal window
suya arch pin set --plan <plan-id> --pin PA5 --signal GPIO_Output --label LED

Configure peripherals

Section titled “Configure peripherals”

Set a peripheral’s mode and parameters:

Terminal window
suya arch peripheral configure --plan <plan-id> --peripheral USART2 --mode Asynchronous

Set clock intent

Section titled “Set clock intent”

Express clock-tree node intent:

Terminal window
suya arch clock set --plan <plan-id> ...

Remove intent

Section titled “Remove intent”

Every assignment has an inverse, for when a pin moves or was mistyped:

Terminal window
suya arch pin rm         --plan <plan-id> --pin PA5
suya arch peripheral rm  --plan <plan-id> --peripheral USART2
suya arch clock rm       --plan <plan-id> --node SYSCLK
suya arch pin-plan rm    --plan <plan-id>          # delete the whole plan

Validate

Section titled “Validate”

Run a structural validation. The headless CubeMX engine on the backend is the authoritative check:

Terminal window
suya arch validate --plan <plan-id>

Generate and commit the .ioc

Section titled “Generate and commit the .ioc”

Generate the .ioc from the plan, then commit it to the connected repo:

Terminal window
suya arch generate --plan <plan-id> --wait  # run headless CubeMX, print the resolved .ioc
suya arch generate-status --run <run-id>    # poll a run started without --wait
suya arch ioc commit                        # generate + commit the .ioc to the connected repo

Without --wait, generate enqueues the run and returns a run id to poll with generate-status. Check status before trusting the result: resolved means the headless CubeMX engine actually ran; unresolved means it did not — the .ioc is your intent, not an engine-validated artifact — and reason says why, most often that no CubeMX image is baked yet for that MCU family.

The .ioc lands in your GitHub repo, ready to open in STM32CubeMX or drive further code generation.

Next steps

Section titled “Next steps”